Tuesday, November 29, 2011

Opprotunities open at Cosmic Circuits

Here are a few interesting opportunites at Cosmic Circuits. If you
know someone then please refer.

Job Description – J1: Digital Designers. Positions are open for people
with expertise in one or more of the following areas –



 Architecture and RTL   :   Behavioural modelling, RTL, Synthesis

 Verification                 :   Functional and Formal

 Back End                   :   Synthesis, P&R ,  Timing closure, EMIR , SI

 Test                          :   ATPG,  Scan and BIST addition,
Coverage enhancements



Exposure to advanced technology nodes (40nm, 28nm)  and their
associated issues is desirable .



Knowledge in high-speed SERDES PHY or Controller design is desirable.

The candidate should possess strong engineering fundamentals, logic in
particular. Should have a grasp of the basics of timing and should
have a working knowledge of Verilog. System Verilog knowledge is a
plus.  Ability to work independently and coordinate with a team is a
must. Knowledge of a scripting language (Python/Perl/Tcl) is a plus.



Working experience :  3–5 years is desirable, though if the candidate
is good, we will make exceptions


Job Description – J2: Digital Design Leads. Positions are open for
people with expertise in one or more of the following areas –



 Architecture and RTL :   Behavioural modelling, RTL, Synthesis

 Verification               :   Functional and Formal

 Back End                 :   Synthesis, P&R ,  Timing closure, EMIR , SI

 Test                         :   ATPG,  Scan and BIST addition,
Coverage enhancements



Exposure to advanced technology nodes (40nm, 28nm)  and their
associated issues is a must .



Knowledge in high-speed SERDES PHY or Controller design is a must.
Standards-body, working-group contributions for any of the popular
SERDES standards is desirable. The candidate should have proven
experience leading RTL/Verification/Back-End/DFT teams.



Working experience :  7+ years is desirable, though if the candidate
is good, we will make exceptions

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