IBM Verification Engineer - ISTL

IBM Verification Engineer - ISTL

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Job description

Verification expertise (chip level and/or block level) - From spec to tape-out for complex designs. 

Test plan/testbench infrastructure/test cases/coverage ownership and execution for multiple projects.

Hands on experience in System Verilog/Specman/Vera or C++.

Knowledge of CPU architecture (inclusive of but not limited to cores/io's/memories and related logic).

System level awareness - integration/initialization/bring-up/DFT is a huge plus. 

Excellent planning/motivation/team playing and communication skills to excel in a multi-site working environment. 

Enthusiasm to learn new functional domains and methodologies.

IBM is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status.

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